This invention relates to bipolar transistors; and in particular, it relates to NPN bipolar transistor logic gates and digital memories which employ various means to achieve a fast switching speed.
In the prior art, both NPN and PNP bipolar transistors have been described. NPN transistors have a collector current which is made primarily of electrons; whereas PNP transistors have a collector current which is made primarily of holes. Electrons are more mobile than holes; and thus where a high speed of operation is a major requirement, NPN transistors are better suited.
For example, in logic circuits and digital memories, high speed is a primary goal. Thus, such circuits are frequently fabricated by using NPN transistors exclusively. Also, by forming those circuits with just one type transistor (NPN), rather than both NPN and PNP, the fabrication process is simplified. This reduces cost since the number of masking steps, as well as the number of implant or diffusion steps is reduced.
However, in logic circuits and digital memories, various parasitic capacitances always exist. They arise, for example, due to the base-substrate junction of the transistor, the emitter-substrate junction of the transistor, and any conductive lines to those junctions. Such parasitic capacitances are troublesome because they limit the speed at which the logic circuits and digital memories can operate.
If a particular design of a logic circuit or digital memory is to be competitive in the marketplace, these parasitic capacitances must be effectively dealt with. Otherwise, the speed at which the circuit operates will be slower than the competition. On the other hand, whatever speed-up means is employed to deal with the parasitic capacitances, it must not be so costly as to be impractical in the marketplace.
Accordingly, a primary object of the invention is to provide an improved speed-up circuit for an NPN bipolar transistor circuit in which parasitic capacitances are effectively dealt with in terms of both switching speed and cost.